1. Field of the Invention
This invention relates to the fabrication of microelectronic devices and, more particularly, to a method for etching a microelectronic topography.
2. Description of the Related Art
The following descriptions and examples are given as background information only.
Plasma etch techniques are often used in the fabrication of microelectronic devices to remove material in a relatively efficient manner. In some cases, the etch rate of plasma processes may be regulated by the application of a bias power coupled to the microelectronic topography. More specifically, power applied to the microelectronic topography may be used to increase the energy of ions residing within a plasma sheath formed between the plasma and the microelectronic topography. In general, an increase in ion energy will cause the ions to bombard the microelectronic topography with more force and at a faster rate, increasing the etch rate of the process. In addition, the power applied to the microelectronic topography may be used to regulate the directionality of the ions within the plasma sheath. In particular, the power applied to the microelectronic topography may bias the ions of the plasma to be projected in a substantially perpendicular direction with respect to the microelectronic topography. In this manner, a plasma etch process may be adapted to produce such an anisotropic etch profile by applying a bias power to the microelectronic topography.
In some cases, however, plasma etch techniques may generate a residue along the periphery of the etched topography. Such a residue may include compounds formed from the reaction of the plasma with the microelectronic topography. Consequently, the composition of the residue may depend on the etch chemistry and the material etched from the microelectronic topography. For example, the residue may include chlorinated, hydrogenated, fluorinated, or oxygenated compounds including silicon or metal molecules. In cases in which a photoresist layer is used to pattern the microelectronic topography, the residue may further include carbon.
In any case, the generation of residue may be particularly prevalent in etching processes which form nonvolatile compounds. In particular, nonvolatile compounds may be less likely to be removed from a reaction chamber due to the relatively low volatility. Consequently, nonvolatile compounds may be more likely to accumulate upon surfaces of a microelectronic topography during an etch process. In general, a nonvolatile compound, as used herein, may refer to a compound which has boiling point greater than approximately 300xc2x0 C. at standard pressure. In some cases, the definition of a nonvolatile compound, as used herein, may be restricted to compounds which have a boiling point greater than approximately 900xc2x0 C. at standard pressure. Examples of some nonvolatile compounds include, for instance, nickel chloride, cobalt chloride, iron chloride, and tungsten chloride. As such, the generation of residue may be particularly prevalent in etching processes which pattern microelectronic topographies which include nickel, cobalt, iron, and/or tungsten metals, since chlorinated gases arc commonly used in plasma etch processes. For example, the generation of residue may be prevalent in the etching process of a magnetic junction of a magnetic random access memory (MRAM) device.
In any case, the residue formed during a plasma etch process may build up along the etched topography, reducing the anisotropic profile of patterned structures. Consequently, the accumulation of residue may cause a structure to be formed having dimensions outside the design specifications of the device. In cases in which the residue includes metal, the residue may further generate a condition sometimes referred to as veiling. In general, veiling may refer to the re-deposition of metal molecules along a periphery of an etched topography. Consequently, such a condition may, in some embodiments, cause metal layers spaced within an etched topography to short with each other, undesirably affecting the operation of a device formed therefrom. For example, veiling along a magnetic junction of an MRAM device may cause a short between magnetic layers of the magnetic junction, reducing the ability to determine the logic state of the junction.
One manner with which to remove residue along a periphery of an etched topography is to clean the topography with an acidic or basic chemistry subsequent to the etching process. Such a cleaning process, however, may also remove portions of the patterned microelectronic topography, altering the dimensions of the device from its design specifications. Such a change in the dimensions of the structure may be particularly undesirable in the fabrication of a magnetic junction of an MRAM device. In particular, cleaning a patterned magnetic junction with an acidic or basic chemistry to remove residue build-up may further reduce the dimensions of the magnetic junction, increasing the resistance of the junction. An increase in the resistance of a magnetic junction may undesirably decrease the tunneling magneto-resistance ratio (TMR) of the junction, reducing the reliability of the device.
Therefore, it may be advantageous to develop a method for etching a microelectronic topography which reduces or eliminates the generation of residue buildup along a periphery of the etched topography. In particular, it may be advantageous to develop a method which removes etch process byproducts during the etch process of a microelectronic topography. In this manner, a cleaning step using an acidic or basic chemistry may not be needed subsequent to the etch process for the fabrication of the device and, therefore, the dimensions of an etch topography may be maintained for the fabrication of a device therefrom.
The problems outlined above may be in large part addressed by a method for etching a microelectronic topography within a plasma reaction chamber. In particular, the method may include pulsing power applied to the microelectronic topography between a high level and a low level. In a preferred embodiment, the high level may be sufficient to form etch byproducts at a faster rate than a rate of removal of the etch byproducts from the plasma reaction chamber at the high level. In contrast, the low level is preferably sufficient to form etch byproducts at a rate that is less than a rate of removal of the etch byproducts at the low level. For example, in some cases, the high and low levels of the power applied to the microelectronic topography may include on and off states, respectively. Alternatively, the high and low levels of the power applied to the microelectronic topography may include different levels of an on state.
In either case, the high level may be a level sufficient to etch the microelectronic topography with a plasma generated within a reaction chamber including the microelectronic topography and the low level may be a level sufficient to stop etching the microelectronic topography with the plasma, in some embodiments. Alternatively, the low level may be sufficient to etch the microelectronic topography at a lower rate relative to the formation rate at the high level. In either case, the power applied to the microelectronic topography may be pulsed such that the strength of a plasma sheath between the plasma and the microelectronic topography may alternate between high and low levels of ion energy. For example, in some cases, the high level of power may be sufficient to generate an ion energy greater than approximately 150 eV, while the low level may be sufficient to generate an ion energy less than approximately 100 eV. Larger or smaller ion density values, however, may be induced by the high and low power levels, depending on the design specifications of the device. In any case, pulsing the power between the high and low levels may include a modulation frequency between approximately 10 Hz and approximately 100 KHz. In addition, the step of pulsing may include a duty ratio between approximately 10% and approximately 90%.
In any case, the etch byproducts formed during the method described herein may be removed from the chamber such that an etched topography may be formed without an accumulation of residue upon its upper surface. More specifically, the method may include reducing the power applied to the microelectronic topography to a level such that the etch byproducts formed at the high level of power may be removed from the reaction chamber during the etch process. Such a removal of etch byproducts may, in some embodiments, include removing the etch byproducts residing within the plasma and/or plasma sheath of the etch process. In this manner, reducing the level of the power applied to the microelectronic topography may prevent the re-deposition of the etch byproducts upon the topography and, therefore, may prevent an accumulation of etch byproducts upon the topography. In addition or alternatively, reducing the power may include removing an accumulation of the etch byproducts which have deposited upon the microelectronic topography.
In any case, the method described herein may be particularly beneficial in an embodiment in which the etch byproducts include a plurality of nonvolatile compounds. In particular, oscillating the power between high and low levels may be beneficial for allowing nonvolatile compounds to be removed from a reaction chamber during an etch process. In such a case, the method may include applying power to a microelectronic topography which is adapted to form a plurality of nonvolatile compounds with a plasma. In addition, the method may include reducing the power to a level sufficient to reduce a concentration of the nonvolatile compounds within the reaction chamber and successively repeating the steps of applying and reducing a plurality of times.
In some cases, the microelectronic topography etched using the method described herein may include a stack of layers used to form a magnetic junction of a magnetic random access memory (MRAM) device. As such, the method may, in some cases, include etching a magnetic layer of the magnetic junction. In addition or alternatively, the method may include etching a metal cap layer of the magnetic junction. Furthermore, the method may alternatively or additionally include etching a tunneling layer of the magnetic junction. In yet other embodiments, the method described herein may be used for patterning all of the layers of a magnetic junction. Consequently, a method for fabricating a magnetic junction of an MRAM device is contemplated herein. More specifically, a method is provided which includes pulsing a bias power applied to a microelectronic topography during a patterning process of a stack of layer such that a magnetic junction is formed with a periphery that is substantially absent of nonvolatile compounds. In any case, the patterning process may include using a photo resist mask or a hard mask layer to pattern the microelectronic topography. In addition, the method may include cleaning the microelectronic topography using a chemistry consisting essentially of deionized water in succession to the step of patterning the topography.
There may be several advantages to etching a microelectronic topography using the method described herein. In particular, a topography may be patterned without an accumulation of etch byproducts along its periphery using the method described herein. Consequently, a cleaning process which uses an acidic or basic chemistry may not be needed for the fabrication of the device. As a result, a patterned structure may be fabricated having dimensions within the design specifications of the device. In particular, a magnetic junction of an MRAM device may be fabricated with dimensions that comply with the design specifications of the device, such that the resistance of the junction is not undesirably large. In addition, the magnetic junction may be patterned without including veiling along the sidewalls of the junction. Consequently, shorts between the layers of the magnetic junction may be avoided.